diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-07-21 21:50:34 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-07-21 21:50:34 +0000 |
| commit | 573f7d40be086b35b25d242818ae0e9c26d05022 (patch) | |
| tree | 831bf36c8294b2dd1362af4e6de3b3f0df0fff50 /src/southbridge/intel/i82801gx/acpi/ich7.asl | |
| parent | 71a3d96bc487f66c84ac869a1215b8a4a4499bf2 (diff) | |
Intel ICH7 updates
- code restructuring (move ich7 out of i945)
- ACPI fixes
- major SMI handler updates
- make sure SMBus lives where we expect it
- try to get usb debug working
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801gx/acpi/ich7.asl')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7.asl | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 2e7233d948..dd3bc87e2f 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -92,7 +92,8 @@ Scope(\) Offset(0x38), // GPIO Level 2 , 5, GP37, 1, // PATA_PWR_EN - , 2, + GP38, 1, // Battery / Power (?) + GP39, 1, // ?? GL05, 8, GL06, 8, GL07, 8 @@ -100,7 +101,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, 0xfff1000, 0x4000) + OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone @@ -111,12 +112,22 @@ Scope(\) , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) - , 1, + , 1, // Reserved PATD, 1, // PATA disable SATD, 1, // SATA disable SMBD, 1, // SMBUS disable HDAD, 1, // Azalia disable - , 11, // ... FIXME + A97D, 1, // AC'97 disable + M97D, 1, // AC'97 disable + ILND, 1, // Internal LAN disable + US1D, 1, // UHCI #1 disable + US2D, 1, // UHCI #2 disable + US3D, 1, // UHCI #3 disable + US4D, 1, // UHCI #4 disable + , 2, // Reserved + LPBD, 1, // LPC bridge disable + EHCD, 1, // EHCI disable + Offset(0x341a), // FD Root Ports RP1D, 1, // Root Port 1 disable RP2D, 1, // Root Port 2 disable RP3D, 1, // Root Port 3 disable @@ -139,6 +150,9 @@ Include ("../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl") // PCI Bridge Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl") +// AC97 Audio and Modem +Include ("../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl") + // LPC Bridge Include ("../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl") |