diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-01 22:23:57 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-21 18:23:54 +0000 |
| commit | 7a2cb35262bedec9e6470bf7fbebf9256e855cff (patch) | |
| tree | 0652f3c41ec3fc694138aa812613b682eb00d793 /src/southbridge/intel/i82801gx/Makefile.inc | |
| parent | 53a343e65b2d452c4a88e6c910a4621c3ced660e (diff) | |
i945/pineview/x4x/i82801gx: Use common code for early SMBus
The early SMBus code for this southbridge checked if the PCI device ID
is valid. However, we can't easily do that in common code, and we should
not attempt to do so either: if a SMBus device behaves differently, then
it should not be using the common code anyway.
Since this southbridge is used with two different northbridges, we need
to update both of them. Plus, x4x raminit no longer needs to know which
southbridge it is paired with, since both i82801gx and i82801jx use the
common early SMBus code, so we drop some preprocessor around includes.
Change-Id: Ic60a3f89bda6000fbe646461f05240c1b09db6e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42005
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/i82801gx/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 1630f939d2..11a9c0007d 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -23,7 +23,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c romstage-y += early_init.c -romstage-y += early_smbus.c romstage-y += early_cir.c endif |