printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 9 insertions, 9 deletions

diff --git a/src/southbridge/intel/i82801ex/i82801ex_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c
index 60b1f304c2..17da5d94c6 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ehci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c
@@ -9,12 +9,12 @@ static void ehci_init(struct device *dev)
 {
 	uint32_t cmd;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, 
 		cmd | PCI_COMMAND_MASTER);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/i82801ex/i82801ex_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c
index b4d2311e0b..cd622907ab 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ide.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c
@@ -13,7 +13,7 @@ static void ide_init(struct device *dev)
 	pci_write_config8(dev, 0x48, 0x05);
 	pci_write_config16(dev, 0x4a, 0x0101);
 	pci_write_config16(dev, 0x54, 0x5055);
-	printk_debug("IDE Enabled\n");
+	printk(BIOS_DEBUG, "IDE Enabled\n");
 }
 
 static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
index b9d19074a4..b97af3860a 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
@@ -233,7 +233,7 @@ static void enable_hpet(struct device *dev)
 	dword |= (code<<15);
 	pci_write_config32(dev, GEN_CNTL, dword);
 
-	printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) );
+	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
 }
 
 static void lpc_init(struct device *dev)
@@ -267,7 +267,7 @@ static void lpc_init(struct device *dev)
 		byte |= 1;
 	}
 	pci_write_config8(dev, 0xa4, byte);
-	printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+	printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
 
 	/* Set up the PIRQ */
 	i82801ex_pirq_init(dev);
diff --git a/src/southbridge/intel/i82801ex/i82801ex_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c
index 73f5773fd5..a490f2a8c3 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_sata.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c
@@ -7,7 +7,7 @@
 
 static void sata_init(struct device *dev)
 {
-  	printk_debug("SATA init\n");
+  	printk(BIOS_DEBUG, "SATA init\n");
 	/* SATA configuration */
 	pci_write_config8(dev, 0x04, 0x07);
 	pci_write_config8(dev, 0x09, 0x8f);
diff --git a/src/southbridge/intel/i82801ex/i82801ex_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c
index 177b82089c..fe80079d09 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_uhci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c
@@ -10,13 +10,13 @@ static void uhci_init(struct device *dev)
 	uint32_t cmd;
 
 #if 1
-	printk_debug("UHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, 
 		cmd | PCI_COMMAND_MASTER);
 
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 
 }
diff --git a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
index 44a701823a..205ea87d94 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
@@ -24,6 +24,6 @@ void watchdog_off(void)
         /* Clear TCO timeout status */
         outw(0x0008, base + 0x04);
         outw(0x0002, base + 0x06);
-        printk_debug("Watchdog ICH5 disabled\r\n");
+        printk(BIOS_DEBUG, "Watchdog ICH5 disabled\r\n");
 }