diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-05-26 12:20:19 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-21 02:06:12 +0100 |
| commit | 721f2998a5d4143f7d609e79255d570b43d804a4 (patch) | |
| tree | 38323779ba458202158c2d3e9655045d79834970 /src/southbridge/intel/i82801ex/ide.c | |
| parent | 6b95406ff3d44679d2e0139236c134655b12b927 (diff) | |
imgtec/pistachio: DDR2, DDR3: DLL reset set
Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801ex/ide.c')
0 files changed, 0 insertions, 0 deletions