diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-02-27 01:50:21 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-02-27 01:50:21 +0000 |
| commit | 138be8315b63b0c8955159580d085e7621882b95 (patch) | |
| tree | aabbcab390ea1e522524ff7e98d11ac752a051b5 /src/southbridge/intel/i82801ex/chip.h | |
| parent | be07eb29bc087a97903f72c2253442c285ce5942 (diff) | |
This does the following:
cd coreboot/src/southbridge
svn mv i82801ca i82801cx
svn mv i82801dbm i82801dx
svn mv i82801er i82801ex
svn copy i82801xx i82801bx
svn mv i82801xx i82801ax
Plus, fixing up the filenames in these directories and the romstage.c and
Kconfig files of the mainboards using those drivers.
Plus, switching the thomson ip1000 and rca rm4100 to the i82801dx driver.
There's a lot more to be done, like
- adding device IDs for the ICH3 and newer drivers that have been kept in
i82801xx so far
- drop the additional parts support from the ax and bx drivers.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801ex/chip.h')
| -rw-r--r-- | src/southbridge/intel/i82801ex/chip.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h new file mode 100644 index 0000000000..34a0a97ffd --- /dev/null +++ b/src/southbridge/intel/i82801ex/chip.h @@ -0,0 +1,36 @@ +#ifndef I82801EX_CHIP_H +#define I82801EX_CHIP_H + +struct southbridge_intel_i82801ex_config +{ + +#define ICH5R_GPIO_USE_MASK 0x03 +#define ICH5R_GPIO_USE_DEFAULT 0x00 +#define ICH5R_GPIO_USE_AS_NATIVE 0x01 +#define ICH5R_GPIO_USE_AS_GPIO 0x02 + +#define ICH5R_GPIO_SEL_MASK 0x0c +#define ICH5R_GPIO_SEL_DEFAULT 0x00 +#define ICH5R_GPIO_SEL_OUTPUT 0x04 +#define ICH5R_GPIO_SEL_INPUT 0x08 + +#define ICH5R_GPIO_LVL_MASK 0x30 +#define ICH5R_GPIO_LVL_DEFAULT 0x00 +#define ICH5R_GPIO_LVL_LOW 0x10 +#define ICH5R_GPIO_LVL_HIGH 0x20 +#define ICH5R_GPIO_LVL_BLINK 0x30 + +#define ICH5R_GPIO_INV_MASK 0xc0 +#define ICH5R_GPIO_INV_DEFAULT 0x00 +#define ICH5R_GPIO_INV_OFF 0x40 +#define ICH5R_GPIO_INV_ON 0x80 + + /* GPIO use select */ + unsigned char gpio[64]; + unsigned int pirq_a_d; + unsigned int pirq_e_h; +}; +extern struct chip_operations southbridge_intel_i82801ex_ops; + +#endif /* I82801EX_CHIP_H */ + |