diff options
author | Steven J. Magnani <steve@digidescorp.com> | 2005-09-21 13:50:38 +0000 |
---|---|---|
committer | Steven J. Magnani <steve@digidescorp.com> | 2005-09-21 13:50:38 +0000 |
commit | b3d2d4d4412425bae14d810bfc4c10ae7d08043a (patch) | |
tree | 48b8a86cef3abf1c7aee0046fb906a8d10eba69f /src/southbridge/intel/i82801er | |
parent | 7557331605ecdcff1276979948dc8c4daf3ed2c3 (diff) |
Rewrite i82801er_enable to do nothing if device does not have an enable/disable bit.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801er')
-rw-r--r-- | src/southbridge/intel/i82801er/i82801er.c | 88 |
1 files changed, 49 insertions, 39 deletions
diff --git a/src/southbridge/intel/i82801er/i82801er.c b/src/southbridge/intel/i82801er/i82801er.c index 79ad25e8b0..1fff0aad0e 100644 --- a/src/southbridge/intel/i82801er/i82801er.c +++ b/src/southbridge/intel/i82801er/i82801er.c @@ -6,48 +6,58 @@ void i82801er_enable(device_t dev) { - device_t lpc_dev; - unsigned int index; - uint16_t reg_old, reg; - -// all 82801er device ares in bus 0 - unsigned int devfn; - devfn = PCI_DEVFN(0x1f, 0); // lpc - lpc_dev = dev_find_slot(0, devfn); // 0 - if (!lpc_dev ) { + unsigned int index = 0; + uint8_t bHasDisableBit = 0; + uint16_t cur_disable_mask, new_disable_mask; + +// all 82801er devices are in bus 0 + unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc + device_t lpc_dev = dev_find_slot(0, devfn); // 0 + if (!lpc_dev) return; - } -#if 0 - if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || - (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_1F0)) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_1F0 << 16))) { - return; + + // Calculate disable bit position for specified device:function + // NOTE: For ICH-5, only the following devices can be disabled: + // D31: F0, F1, F2, F3, F5, F6, + // D29: F0, F1, F2, F3, F7 + + if (PCI_SLOT(dev->path.u.pci.devfn) == 31) { + index = PCI_FUNC(dev->path.u.pci.devfn); + + switch (index) { + case 0: + case 1: + case 2: + case 3: + case 5: + case 6: + bHasDisableBit = 1; + break; + + default: + break; + }; + + if (index == 0) + index = 14; // D31:F0 bit is an exception + + } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) { + index = 8 + PCI_FUNC(dev->path.u.pci.devfn); + + if ((PCI_FUNC(dev->path.u.pci.devfn) < 4) || (PCI_FUNC(dev->path.u.pci.devfn) == 7)) + bHasDisableBit = 1; + } + + if (bHasDisableBit) { + cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); + new_disable_mask = cur_disable_mask & ~(1<<index); // enable it + if (!dev->enabled) { + new_disable_mask |= (1<<index); // disable it + } + if (new_disable_mask != cur_disable_mask) { + pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); } } -#endif - - index = (dev->path.u.pci.devfn & 7); - if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f - if(index==0){ //1f0 - index = 14; - } - } else { // D=0x1d - index += 8; - } - - reg_old = pci_read_config16(lpc_dev, FUNC_DIS); - reg = reg_old; - reg &= ~(1<<index); // enable it - if (!dev->enabled) { - reg |= (1<<index); // disable it - } - if (reg != reg_old) { - pci_write_config16(lpc_dev, FUNC_DIS, reg); - } - reg = pci_read_config16(lpc_dev, FUNC_DIS); - } struct chip_operations southbridge_intel_i82801er_ops = { |