diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-08 11:31:19 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-22 14:16:38 +0000 |
| commit | 682613f0653064eeeba2b4d15f6d50e32a692bd3 (patch) | |
| tree | f53d9721eab49251b9ffda596f2b6d62e239e31d /src/southbridge/intel/i82801dx | |
| parent | ea6d12a0de8af000fb72a873b63364462f280643 (diff) | |
sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()
This adds delivery of PIC/i8259 interrupts via ExtNMI on the
affected platfoms.
Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 321c605366..34d93c4800 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -48,7 +48,7 @@ static void i82801dx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); ioapic_set_boot_config(VIO_APIC_VADDR, true); } |