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authorPatrick Rudolph <siro@das-labor.org>2018-10-01 19:17:11 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:35:25 +0000
commit45022ae056cdbf58429b77daf2da176306312801 (patch)
tree4218666e3c14e41232778c4ceff301292b3c61d9 /src/southbridge/intel/i82801dx
parent33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff)
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
-rw-r--r--src/southbridge/intel/i82801dx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801dx/Makefile.inc2
-rw-r--r--src/southbridge/intel/i82801dx/reset.c23
3 files changed, 0 insertions, 26 deletions
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index 19e890f58b..827f6bb0f6 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -18,7 +18,6 @@ config SOUTHBRIDGE_INTEL_I82801DX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG
select SOUTHBRIDGE_INTEL_COMMON
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index c51488390d..7d87995259 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -24,8 +24,6 @@ ramstage-y += lpc.c
ramstage-y += usb.c
ramstage-y += usb2.c
-ramstage-y += reset.c
-
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c
deleted file mode 100644
index 1839ad6f9a..0000000000
--- a/src/southbridge/intel/i82801dx/reset.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_hard_reset(void)
-{
- /* Try rebooting through port 0xcf9 */
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}