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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-29 06:26:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-01-18 07:21:34 +0000
commit661ad4666ca0e78195f6901fce7b44a7e56e6331 (patch)
tree57c25cee551ec747dcfdf0e38f995a091d5fcd79 /src/southbridge/intel/i82801dx
parent286a0572e75ade325238617d15c136f74c4f67a4 (diff)
ACPI: Select ACPI_SOC_NVS only where suitable
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
Diffstat (limited to 'src/southbridge/intel/i82801dx')
-rw-r--r--src/southbridge/intel/i82801dx/fadt.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c
index 66aa3f1ba9..84ea73ad9c 100644
--- a/src/southbridge/intel/i82801dx/fadt.c
+++ b/src/southbridge/intel/i82801dx/fadt.c
@@ -2,7 +2,6 @@
#include <device/pci_ops.h>
#include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
#include <version.h>
/* FIXME: This needs to go into a separate .h file
@@ -80,8 +79,3 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.addrl = pmbase + 0x28;
fadt->x_gpe0_blk.addrh = 0x0;
}
-
-size_t gnvs_size_of_array(void)
-{
- return 0;
-}