sb/intel/i82801dx: Drop GNVS in SMM

The table in CBMEM was never allocated with i82801dx.

Change-Id: I4ad97f6504e0f1b22d16210b7dbf5164852cb232
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42851
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 1 insertions, 188 deletions

diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h
deleted file mode 100644
index 1f8f6d1ad1..0000000000
--- a/src/southbridge/intel/i82801dx/nvs.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOUTHBRIDGE_INTEL_I82801DX_NVS_H
-#define SOUTHBRIDGE_INTEL_I82801DX_NVS_H
-
-#include <stdint.h>
-
-struct __packed global_nvs {
-	/* Miscellaneous */
-	u16	osys; /* 0x00 - Operating System */
-	u8	smif; /* 0x02 - SMI function call ("TRAP") */
-	u8	prm0; /* 0x03 - SMI function call parameter */
-	u8	prm1; /* 0x04 - SMI function call parameter */
-	u8	scif; /* 0x05 - SCI function call (via _L00) */
-	u8	prm2; /* 0x06 - SCI function call parameter */
-	u8	prm3; /* 0x07 - SCI function call parameter */
-	u8	lckf; /* 0x08 - Global Lock function for EC */
-	u8	prm4; /* 0x09 - Lock function parameter */
-	u8	prm5; /* 0x0a - Lock function parameter */
-	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
-	u8	lids; /* 0x0f - LID state (open = 1) */
-	u8	pwrs; /* 0x10 - Power state (AC = 1) */
-	u8	dbgs; /* 0x11 - Debug state */
-	u8	linx; /* 0x12 - Linux OS */
-	u8	dckn; /* 0x13 - PCIe docking state */
-	/* Thermal policy */
-	u8	actt; /* 0x14 - active trip point */
-	u8	psvt; /* 0x15 - passive trip point */
-	u8	tc1v; /* 0x16 - passive trip point TC1 */
-	u8	tc2v; /* 0x17 - passive trip point TC2 */
-	u8	tspv; /* 0x18 - passive trip point TSP */
-	u8	crtt; /* 0x19 - critical trip point */
-	u8	dtse; /* 0x1a - Digital Thermal Sensor enable */
-	u8	dts1; /* 0x1b - DT sensor 1 */
-	u8	dts2; /* 0x1c - DT sensor 2 */
-	u8	rsvd2;
-	/* Battery Support */
-	u8	bnum; /* 0x1e - number of batteries */
-	u8	b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */
-	u8	b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
-	u8	rsvd3[3];
-	/* Processor Identification */
-	u8	apic; /* 0x28 - APIC enabled */
-	u8	mpen; /* 0x29 - MP capable/enabled */
-	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
-	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
-	u8	ppcm; /* 0x2c - Max. PPC state */
-	u8	rsvd4[5];
-	/* Super I/O & CMOS config */
-	u8	natp; /* 0x32 - SIO type */
-	u8	cmap; /* 0x33 - */
-	u8	cmbp; /* 0x34 - */
-	u8	lptp; /* 0x35 - LPT port */
-	u8	fdcp; /* 0x36 - Floppy Disk Controller */
-	u8	rfdv; /* 0x37 - */
-	u8	hotk; /* 0x38 - Hot Key */
-	u8	rtcf;
-	u8	util;
-	u8	acin;
-	/* Integrated Graphics Device */
-	u8	igds; /* 0x3c - IGD state */
-	u8	tlst; /* 0x3d - Display Toggle List Pointer */
-	u8	cadl; /* 0x3e - currently attached devices */
-	u8	padl; /* 0x3f - previously attached devices */
-	u16	rsvd14[3];
-	u8	ndid; /* 0x46 - number of device ids */
-	u32	did[5]; /* 0x47 - 5b device id 1..5 */
-	u8	rsvd5[0x9];
-	/* Backlight Control */
-	u8	blcs; /* 0x64 - Backlight Control possible */
-	u8	brtl;
-	u8	odds;
-	u8	rsvd6[0x7];
-	/* Ambient Light Sensors*/
-	u8	alse; /* 0x6e - ALS enable */
-	u8	alaf;
-	u8	llow;
-	u8	lhih;
-	u8	rsvd7[0x6];
-	/* EMA */
-	u8	emae; /* 0x78 - EMA enable */
-	u16	emap;
-	u16	emal;
-	u8	rsvd8[0x5];
-	/* MEF */
-	u8	mefe; /* 0x82 - MEF enable */
-	u8	rsvd9[0x9];
-	/* TPM support */
-	u8	tpmp; /* 0x8c - TPM */
-	u8	tpme;
-	u8	rsvd10[8];
-	/* SATA */
-	u8	gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
-	u8	gtf1[7];
-	u8	gtf2[7];
-	u8	idem;
-	u8	idet;
-	u8	rsvd11[67];
-	/* Mainboard specific */
-	u8	dock; /* 0xf0 - Docking Status */
-	u8	bten;
-	u8	rsvd13[14];
-};
-
-#endif /* SOUTHBRIDGE_INTEL_I82801DX_NVS_H */
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 7cd5c7056c..b54d1d39c5 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -19,8 +19,6 @@
 #define   G_SMRANE	(1 << 3)
 #define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
-#include "nvs.h"
-
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
  */
@@ -30,13 +28,6 @@ unsigned char *mbi = NULL;
 u32 mbi_len;
 u8 mbi_initialized = 0;
 
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
- * by coreboot.
- */
-struct global_nvs *gnvs = (struct global_nvs *)0x0;
-void *tcg = (void *)0x0;
-void *smi1 = (void *)0x0;
-
 /**
  * @brief read and clear PM1_STS
  * @return PM1_STS register
@@ -188,23 +179,6 @@ static void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-int southbridge_io_trap_handler(int smif)
-{
-	switch (smif) {
-	case 0x32:
-		printk(BIOS_DEBUG, "OS Init\n");
-		/* gnvs->smif:
-		 *  On success, the IO Trap Handler returns 0
-		 *  On failure, the IO Trap Handler returns a value != 0
-		 */
-		gnvs->smif = 0;
-		return 1; /* IO trap handled */
-	}
-
-	/* Not handled */
-	return 0;
-}
-
 /**
  * @brief Set the EOS bit
  */
@@ -482,62 +456,6 @@ static void southbridge_smi_periodic(void)
 	printk(BIOS_DEBUG, "Periodic SMI.\n");
 }
 
-static void southbridge_smi_monitor(void)
-{
-#define IOTRAP(x) (trap_sts & (1 << x))
-#if 0
-	u32 trap_sts, trap_cycle;
-	u32 data, mask = 0;
-	int i;
-
-	trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
-	RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
-
-	trap_cycle = RCBA32(0x1e10);
-	for (i=16; i<20; i++) {
-		if (trap_cycle & (1 << i))
-			mask |= (0xff << ((i - 16) << 2));
-	}
-
-
-	/* IOTRAP(3) SMI function call */
-	if (IOTRAP(3)) {
-		if (gnvs && gnvs->smif)
-			io_trap_handler(gnvs->smif); // call function smif
-		return;
-	}
-
-	/* IOTRAP(2) currently unused
-	 * IOTRAP(1) currently unused */
-
-	/* IOTRAP(0) SMIC */
-	if (IOTRAP(0)) {
-		if (!(trap_cycle & (1 << 24))) { // It's a write
-			printk(BIOS_DEBUG, "SMI1 command\n");
-			data = RCBA32(0x1e18);
-			data &= mask;
-			// if (smi1)
-			//	southbridge_smi_command(data);
-			// return;
-		}
-		// Fall through to debug
-	}
-
-	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
-	for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
-	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
-	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
-	printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
-
-	if (!(trap_cycle & (1 << 24))) {
-		/* Write Cycle */
-		data = RCBA32(0x1e18);
-		printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
-	}
-#endif
-#undef IOTRAP
-}
-
 typedef void (*smi_handler_t)(void);
 
 smi_handler_t southbridge_smi[32] = {
@@ -562,7 +480,7 @@ smi_handler_t southbridge_smi[32] = {
 	NULL,			  // [18] INTEL_USB2_STS
 	NULL,			  // [19] reserved
 	NULL,			  // [20] PCI_EXP_SMI_STS
-	southbridge_smi_monitor,  // [21] MONITOR_STS
+	NULL,			  // [21] MONITOR_STS
 	NULL,			  // [22] reserved
 	NULL,			  // [23] reserved
 	NULL,			  // [24] reserved