diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 22:36:28 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 13:18:14 +0000 |
| commit | 7db5ce15a3fd8a90cc3bc6c08526358257892cb3 (patch) | |
| tree | d488cca798baebaa1487291e1b3412db621d01b5 /src/southbridge/intel/i82801dx | |
| parent | 4787f2953cf48eadb8da5b71e85407bbe5abd8b0 (diff) | |
sb/intel/i82801dx: Drop unneeded PM2 settings from FADT
The PM2_CNT register block is not present on this southbridge, as per
Intel Document 290744 (ICH4 datasheet). Also, the ACPI specification,
version 6.3, section 4.8.1.3 (PM2 Control Register), says:
This register block is optional, if not supported its block pointer and
length contain a value of zero.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.
Also delete a comment about `pm2_cnt_len`, which said that the right
value differs from zero. Looks like that comment was wrong instead.
Change-Id: Icbb32f5db7b368c764b3477c40f8ae9c788df5ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/fadt.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index 52e2566f76..cdab3f44c1 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -32,14 +32,11 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm2_cnt_blk = 0x0; fadt->pm_tmr_blk = pmbase + 0x8; fadt->gpe0_blk = pmbase + 0x28; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; - /* XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) */ - fadt->pm2_cnt_len = 0; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; fadt->p_lvl2_lat = 1; @@ -80,13 +77,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; |