diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-17 17:50:48 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-17 17:50:48 +0000 |
| commit | 07190470053f1e4f937a0d0d100859c452c00fbc (patch) | |
| tree | a2c8e16119c4b1e365d419af78632dadebbc660f /src/southbridge/intel/i82801dx | |
| parent | 50776fab1c9062ddfa353ee6c138f69d901c11b7 (diff) | |
fix HPET on some ICH southbridges
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx_lpc.c | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c index 181f5454e1..8f698ee53d 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c +++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c @@ -177,27 +177,6 @@ static void i82801dx_lpc_decode_en(device_t dev) pci_write_config16(dev, LPC_EN, 0x300F); } -static void enable_hpet(struct device *dev) -{ - u32 reg32; - u32 code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - pci_write_config32(dev, GEN_CNTL, reg32); - - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); -} - static void lpc_init(struct device *dev) { /* Set the value for PCI command register. */ @@ -228,9 +207,6 @@ static void lpc_init(struct device *dev) /* Setup decode ports and LPC I/F enables. */ i82801dx_lpc_decode_en(dev); - - /* Initialize the High Precision Event Timers */ - enable_hpet(dev); } static void i82801dx_lpc_read_resources(device_t dev) |