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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:40:21 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-21 16:29:35 +0000
commit131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef (patch)
treeaccfc86126dba3bf22fe731689ee791894a3bcaa /src/southbridge/intel/i82801dx/smi.c
parentb69bbfe1ef52421f0bbe1e632d99dc264660ee02 (diff)
src/southbridge: Drop unneeded empty lines
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/intel/i82801dx/smi.c')
-rw-r--r--src/southbridge/intel/i82801dx/smi.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c
index 26bbbe143d..dd993cedb0 100644
--- a/src/southbridge/intel/i82801dx/smi.c
+++ b/src/southbridge/intel/i82801dx/smi.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
@@ -13,7 +12,6 @@
#include <string.h>
#include "i82801dx.h"
-
void northbridge_write_smram(u8 smram);
/* For intel/e7505. */
@@ -98,7 +96,6 @@ static void dump_smi_status(u32 smi_sts)
printk(BIOS_DEBUG, "\n");
}
-
/**
* @brief read and clear GPE0_STS
* @return GPE0_STS register
@@ -138,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts)
printk(BIOS_DEBUG, "\n");
}
-
/**
* @brief read and clear ALT_GP_SMI_STS
* @return ALT_GP_SMI_STS register
@@ -164,8 +160,6 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
printk(BIOS_DEBUG, "\n");
}
-
-
/**
* @brief read and clear TCOx_STS
* @return TCOx_STS registers
@@ -184,7 +178,6 @@ static u32 reset_tco_status(void)
return reg32;
}
-
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
@@ -204,8 +197,6 @@ static void dump_tco_status(u32 tco_sts)
printk(BIOS_DEBUG, "\n");
}
-
-
/**
* @brief Set the EOS bit
*/