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authorVarshit Pandya <pandyavarshit@gmail.com>2024-02-22 17:34:32 +0530
committerFelix Held <felix-coreboot@felixheld.de>2024-02-23 14:52:21 +0000
commita138cfb422109018ba35c8f5d82621717eaf0611 (patch)
tree52f00b790c8d282daf79b6a14c92373a68debeea /src/southbridge/intel/i82801dx/lpc.c
parent961ed9fe27108ef46fc6c0f2aad340bb02e09081 (diff)
soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and adds the code to fix up the clock configuration depending on dxio descriptors. Also this brings glinda in line with cezanne, mendocino, phoenix and picasso. This also prepares glinda to use the common function gpp_clk_setup_common. Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801dx/lpc.c')
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