ICH4 update, fix ATA init, drop SATA (chipset doesn't have SATA)

fix some PCI IDs, enable USB bus mastering, add some license headers, ...

LPC code needs another look, but I think we're getting there.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 46 insertions, 24 deletions

diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
index 0a0ff91f34..30d197c461 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
 //#define SMBUS_IO_BASE 0x1000
 //#define SMBUS_IO_BASE 0x0f00
@@ -12,7 +31,7 @@
 #define SMBTRNSADD 0x9
 #define SMBSLVDATA 0xa
 #define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf 
+#define SMBUS_PIN_CTL  0xf
 
 /* Between 1-10 seconds, We should never timeout normally 
  * Longer than this is just painful when a timeout condition occurs.
@@ -28,15 +47,14 @@ static void enable_smbus(void)
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	/* Set smbus enable */
 	pci_write_config8(dev, 0x40, 0x01);
-	/* Set smbus iospace enable */ 
+	/* Set smbus iospace enable */
 	pci_write_config16(dev, 0x4, 0x01);
-	/* Disable interrupt generation */ 
+	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 }
 
-
 static inline void smbus_delay(void)
 {
 	outb(0x80, 0x80);
@@ -53,8 +71,8 @@ static int smbus_wait_until_active(void)
 		if ((val & 1)) {
 			break;
 		}
-	} while(--loops);
-	return loops?0:-4;
+	} while (--loops);
+	return loops ? 0 : -4;
 }
 
 static int smbus_wait_until_ready(void)
@@ -68,12 +86,12 @@ static int smbus_wait_until_ready(void)
 		if ((val & 1) == 0) {
 			break;
 		}
-		if(loops == (SMBUS_TIMEOUT / 2)) {
-			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 
-				SMBUS_IO_BASE + SMBHSTSTAT);
+		if (loops == (SMBUS_TIMEOUT / 2)) {
+			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+			     SMBUS_IO_BASE + SMBHSTSTAT);
 		}
-	} while(--loops);
-	return loops?0:-2;
+	} while (--loops);
+	return loops ? 0 : -2;
 }
 
 static int smbus_wait_until_done(void)
@@ -83,16 +101,16 @@ static int smbus_wait_until_done(void)
 	do {
 		unsigned char val;
 		smbus_delay();
-		
+
 		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ( (val & 1) == 0) {
+		if ((val & 1) == 0) {
 			break;
 		}
-		if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
+		if ((val & ~((1 << 6) | (1 << 0))) != 0) {
 			break;
 		}
-	} while(--loops);
-	return loops?0:-3;
+	} while (--loops);
+	return loops ? 0 : -3;
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)
@@ -101,12 +119,12 @@ static int smbus_read_byte(unsigned device, unsigned address)
 	unsigned char global_status_register;
 	unsigned char byte;
 
-	/*print_err("smbus_read_byte\r\n");*/
+	/*print_err("smbus_read_byte\r\n"); */
 	if (smbus_wait_until_ready() < 0) {
 		print_err_hex8(-2);
 		return -2;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
@@ -115,16 +133,18 @@ static int smbus_read_byte(unsigned device, unsigned address)
 	/* set the command/address... */
 	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
 	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
-	/* clear the data byte...*/
+	/* clear the data byte... */
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
 
 	/* start a byte read, with interrupts disabled */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 	/* poll for it to start */
 	if (smbus_wait_until_active() < 0) {
 		print_err_hex8(-4);
@@ -137,7 +157,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
 		return -3;
 	}
 
-	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
+	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6);	/* Ignore the In Use Status... */
 
 	/* read results of transaction */
 	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
@@ -153,15 +173,17 @@ static int smbus_read_byte(unsigned device, unsigned address)
  */
 	return byte;
 }
+
 #if 0
-static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+static void smbus_write_byte(unsigned device, unsigned address,
+			     unsigned char val)
 {
 	if (smbus_wait_until_ready() < 0) {
 		return;
 	}
 
 	/* by LYH */
-	outb(0x37,SMBUS_IO_BASE + SMBHSTSTAT);
+	outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT);
 	/* set the device I'm talking too */
 	outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);