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authorJoseph Smith <joe@settoplinux.org>2010-03-17 03:37:18 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-17 03:37:18 +0000
commit48f3e2b5e1fa75ff9d43485ac9a620255e1048bf (patch)
treef99492745ffb814c22dfed736b796dd3bb2fb723 /src/southbridge/intel/i82801dx/i82801dx.h
parent0d7a99669545bef76d57d17fd41ab376e061b109 (diff)
This patch fixes up the i82801dx_lpc.c code post transition.
Boot Tested (bootlog attached) Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801dx/i82801dx.h')
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h19
1 files changed, 17 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 070fb7e4a2..cb062bf1d4 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -36,6 +36,9 @@
extern void i82801dx_enable(device_t dev);
#endif
+#define IO_APIC_ADDR 0xfec00000
+#define HPET_ADDR 0xfed00000
+
#define DEBUG_PERIODIC_SMIS 0
#define MAINBOARD_POWER_OFF 0
@@ -79,8 +82,15 @@ extern void i82801dx_enable(device_t dev);
#define BIOS_CNTL 0x4E
#define GPIO_BASE 0x58
#define GPIO_CNTL 0x5C
-#define PIRQA_ROUT 0x60
-#define PIRQE_ROUT 0x68
+#define GPIOBASE_ADDR 0x0500
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
#define COM_DEC 0xE0
#define LPC_EN 0xE6
#define FUNC_DIS 0xF2
@@ -192,4 +202,9 @@ extern void i82801dx_enable(device_t dev);
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD (1 << 2)
+#define RTC_POWER_FAILED (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
#endif /* I82801DX_H */