e7505/i82801dx: Use common code for early SMBus

While it looks different, the early SMBus code for this southbridge is
still the same. In addition, this code was not checking the vendor ID
before. It is assumed that adding this check does not pose a problem.

Change-Id: I95ae4db399ce5592cefca82fa75f349220023b8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42006
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 21 deletions

diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index fc225b0466..76ef1b8a15 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
 #include <device/smbus_host.h>
 #include "i82801dx.h"
 
@@ -9,22 +7,3 @@ void i82801dx_early_init(void)
 {
 	enable_smbus();
 }
-
-uintptr_t smbus_base(void)
-{
-	return CONFIG_FIXED_SMBUS_IO_BASE;
-}
-
-int smbus_enable_iobar(uintptr_t base)
-{
-	pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
-
-	/* set smbus iobase */
-	pci_write_config32(dev, 0x20, base | 1);
-	/* Set smbus enable */
-	pci_write_config8(dev, 0x40, 0x01);
-	/* Set smbus iospace enable */
-	pci_write_config16(dev, 0x4, 0x01);
-
-	return 0;
-}