diff options
author | Ronald G. Minnich <rminnich@gmail.com> | 2004-08-24 16:20:46 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2004-08-24 16:20:46 +0000 |
commit | 182615d635343a33306320833b2606e1f966e35a (patch) | |
tree | 1a2dc8f41d1264a70531bc7c27c8326816deb885 /src/southbridge/intel/i82801dbm/cmos_failover.c | |
parent | c66444c175a6c4c285b0ff93a25991e28e0bd756 (diff) |
new intel io hub.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801dbm/cmos_failover.c')
-rw-r--r-- | src/southbridge/intel/i82801dbm/cmos_failover.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801dbm/cmos_failover.c b/src/southbridge/intel/i82801dbm/cmos_failover.c new file mode 100644 index 0000000000..9702313f9c --- /dev/null +++ b/src/southbridge/intel/i82801dbm/cmos_failover.c @@ -0,0 +1,16 @@ +//kind of cmos_err for ich5 +#define RTC_FAILED (1 <<2) +#define GEN_PMCON_3 0xa4 +static void check_cmos_failed(void) +{ + + uint8_t byte; + byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3); + if( byte & RTC_FAILED){ +//clear bit 1 and bit 2 + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0x0c; + byte |= MAX_REBOOT_CNT << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } +} |