diff options
author | Jon Dufresne <jon.dufresne@gmail.com> | 2006-12-28 12:00:58 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2006-12-28 12:00:58 +0000 |
commit | 9095e30f2dbac3c53a380a20d15d4698449dab20 (patch) | |
tree | 57d7d7634cbaf50885d2010c250eb8151f6b056a /src/southbridge/intel/i82801db/cmos_failover.c | |
parent | a5fc22fd6b45e96534802dd1069060990f4077ff (diff) |
A patch to add initial support for the i82801db southbridge based
heavily on the code for i82801dbm and i82801er
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801db/cmos_failover.c')
-rw-r--r-- | src/southbridge/intel/i82801db/cmos_failover.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801db/cmos_failover.c b/src/southbridge/intel/i82801db/cmos_failover.c new file mode 100644 index 0000000000..5b4bbd2909 --- /dev/null +++ b/src/southbridge/intel/i82801db/cmos_failover.c @@ -0,0 +1,34 @@ +/* + * This file is part of the LinuxBIOS project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +//kind of cmos_err for ich5 +#define RTC_FAILED (1 <<2) +#define GEN_PMCON_3 0xa4 +static void check_cmos_failed(void) +{ + + uint8_t byte; + byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3); + if( byte & RTC_FAILED){ +//clear bit 1 and bit 2 + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0x0c; + byte |= MAX_REBOOT_CNT << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } +} |