diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/intel/i82801cx | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/i82801cx')
| -rw-r--r-- | src/southbridge/intel/i82801cx/lpc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f6c33b7feb..22671c3de3 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -41,13 +41,13 @@ static void i82801cx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } // This is how interrupts are received from the Super I/O chip |