diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-02-27 01:50:21 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-02-27 01:50:21 +0000 |
| commit | 138be8315b63b0c8955159580d085e7621882b95 (patch) | |
| tree | aabbcab390ea1e522524ff7e98d11ac752a051b5 /src/southbridge/intel/i82801cx/i82801cx.h | |
| parent | be07eb29bc087a97903f72c2253442c285ce5942 (diff) | |
This does the following:
cd coreboot/src/southbridge
svn mv i82801ca i82801cx
svn mv i82801dbm i82801dx
svn mv i82801er i82801ex
svn copy i82801xx i82801bx
svn mv i82801xx i82801ax
Plus, fixing up the filenames in these directories and the romstage.c and
Kconfig files of the mainboards using those drivers.
Plus, switching the thomson ip1000 and rca rm4100 to the i82801dx driver.
There's a lot more to be done, like
- adding device IDs for the ICH3 and newer drivers that have been kept in
i82801xx so far
- drop the additional parts support from the ax and bx drivers.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801cx/i82801cx.h')
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx.h | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h new file mode 100644 index 0000000000..b9b3511a4a --- /dev/null +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -0,0 +1,78 @@ +#ifndef I82801CX_H +#define I82801CX_H + +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#include "chip.h" +extern void i82801cx_enable(device_t dev); +#endif + + +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_3 0xa4 + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0x4E +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define PIRQA_ROUT 0x60 +#define PIRQE_ROUT 0x68 +#define COM_DEC 0xE0 +#define LPC_EN 0xE6 +#define FUNC_DIS 0xF2 + +// GEN_PMCON_3 bits +#define RTC_BATTERY_DEAD (1<<2) +#define RTC_POWER_FAILED (1<<1) +#define SLEEP_AFTER_POWER_FAIL (1<<0) + +/********************************************************************/ +/* IDE Controller */ +/********************************************************************/ + +// PCI Configuration Space (D31:F1) +#define IDE_TIM_PRI 0x40 // IDE timings, primary +#define IDE_TIM_SEC 0x42 // IDE timings, secondary + + +// IDE_TIM bits +#define IDE_DECODE_ENABLE (1<<15) + +/********************************************************************/ +/* SMBus */ +/********************************************************************/ + +// PCI Configuration Space (D31:F3) +#define SMB_BASE 0x20 +#define HOSTC 0x40 + +// HOSTC bits +#define I2C_EN (1<<2) +#define SMB_SMI_EN (1<<1) +#define HST_EN (1<<0) + +#define SMBUS_IO_BASE 0x1000 + +// I/O registers (relative to SMBUS_IO_BASE) +#define SMBHSTSTAT 0 +#define SMBHSTCTL 2 +#define SMBHSTCMD 3 +#define SMBXMITADD 4 +#define SMBHSTDAT0 5 +#define SMBHSTDAT1 6 +#define SMBBLKDAT 7 +#define SMBTRNSADD 9 +#define SMBSLVDATA 10 +#define SMLINK_PIN_CTL 14 +#define SMBUS_PIN_CTL 15 + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000) + +#endif /* I82801CX_H */ |