printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 10 insertions, 10 deletions

diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c
index 9bfab00399..ffbaf80dbd 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_ide.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c
@@ -43,9 +43,9 @@ static void ide_init(struct device *dev)
 	if (!config || config->ide0_enable) {
 		/* Enable primary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE0: Primary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE0: Primary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -54,9 +54,9 @@ static void ide_init(struct device *dev)
 	if (!config || config->ide1_enable) {
 		/* Enable secondary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE1: Secondary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE1: Secondary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }
diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
index 0d7e09c931..c63de08c2a 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
@@ -92,14 +92,14 @@ void i82801bx_enable_apic(struct device *dev)
 	reg32 |= (1 << 1);	/* Delayed transaction enable */
 	reg32 |= (1 << 2);	/* DMA collection buffer enable */
 	pci_write_config32(dev, GEN_CNTL, reg32);
-	printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
 	*ioapic_index = 0;
 	*ioapic_data = (1 << 25);
 
 	*ioapic_index = 0;
 	reg32 = *ioapic_data;
-	printk_debug("Southbridge APIC ID = %x\n", reg32);
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
 	if (reg32 != (1 << 25))
 		die("APIC Error\n");
 
@@ -189,7 +189,7 @@ static void i82801bx_power_options(device_t dev)
 	 * 1 == S5 Soft Off
 	 */
 	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-	printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
+	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
 
 	/* Set up NMI on errors. */
 	byte = inb(0x61);
diff --git a/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c
index 1e885e920d..29034444b4 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c
@@ -30,11 +30,11 @@ static void usb_ehci_init(struct device *dev)
 	/* TODO: Is any special init really needed? */
 	uint32_t cmd;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
diff --git a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
index aea10e1c7b..fb45f521c5 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
@@ -50,5 +50,5 @@ void watchdog_off(void)
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
 
-	printk_debug("ICH Watchdog disabled\r\n");
+	printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n");
 }