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authorAaron Durbin <adurbin@chromium.org>2016-03-18 12:21:23 -0500
committerAaron Durbin <adurbin@chromium.org>2016-03-23 14:24:30 +0100
commit7f8afe063139f6fc7076a3e4edf6093a953792dc (patch)
treeb7d0c8d6372abe5b96bc37068e3e132ab97b8ea7 /src/southbridge/intel/i82801bx/smbus.c
parent2b239485358ec063a4803f248c88378076810e24 (diff)
arch/x86: introduce postcar stage/phase
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801bx/smbus.c')
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