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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-12-12 09:22:34 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 06:36:21 +0100 |
| commit | 138f2cede491b65cfd8c73b9185a2dc7ee10b8b3 (patch) | |
| tree | f429c33a4286531502f237403fa4d77d5d74389c /src/southbridge/intel/i82801ax | |
| parent | 89f79a019fd049f26ed7bf40618ff960bd9e095e (diff) | |
haswell: remove GPIO60 memory reset gate on S3 transition
This is no longer tied to a GPIO but has a proper chipset pin.
Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2643
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801ax')
0 files changed, 0 insertions, 0 deletions