Intel 82801ax/82801bx: Fix and hook up i82801xx_smbus.c.

 - Fix incorrect #includes, add missing ones.

 - Drop unused do_smbus_write_block() and smbus_wait_until_blk_done().

 - Pass smbus_io_base to all functions as the other ICH implementations do.

 - Random other fixes which are required to make it build.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 32 insertions, 121 deletions

diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc
index 4d2288adc3..6d253f01fe 100644
--- a/src/southbridge/intel/i82801ax/Makefile.inc
+++ b/src/southbridge/intel/i82801ax/Makefile.inc
@@ -23,11 +23,9 @@ driver-y += i82801ax_ac97.c
 driver-y += i82801ax_ide.c
 driver-y += i82801ax_lpc.c
 driver-y += i82801ax_pci.c
-# driver-y += i82801ax_smbus.c
+driver-y += i82801ax_smbus.c
 driver-y += i82801ax_usb.c
 
 ramstage-y += i82801ax_reset.c
 ramstage-y += i82801ax_watchdog.c
 
-# TODO: Fix and enable i82801ax_smbus.o later.
-
diff --git a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
index 14fa924bea..d313613cea 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
@@ -63,19 +63,6 @@ static void enable_smbus(void)
 
 static inline int smbus_read_byte(unsigned device, unsigned address)
 {
-	return do_smbus_read_byte(device, address);
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
-static void smbus_write_byte(unsigned device, unsigned address,
-			     unsigned char val)
-{
-	print_err("Unimplemented smbus_write_byte() called\n");
-	return;
-}
-
-static inline int smbus_write_block(unsigned device, unsigned length,
-				    unsigned cmd, unsigned data1,
-				    unsigned data2)
-{
-	return do_smbus_write_block(device, length, cmd, data1, data2);
-}
diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_smbus.c
index 6661993324..af7c3e110d 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_smbus.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.c
@@ -19,25 +19,28 @@
  */
 
 #include <stdint.h>
-#include <smbus.h>
-#include <pci.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
 #include <arch/io.h>
 #include "i82801ax.h"
-#include "i82801_smbus.h"
+#include "i82801ax_smbus.h"
 
-static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
+static int lsmbus_read_byte(device_t dev, u8 address)
 {
-	unsigned device;	/* TODO: u16? */
+	u16 device;
 	struct resource *res;
+	struct bus *pbus;
 
 	device = dev->path.i2c.device;
-	res = find_resource(bus->dev, 0x20);
+	pbus = get_pbus_smbus(dev);
+	res = find_resource(pbus->dev, 0x20);
 
 	return do_smbus_read_byte(res->base, device, address);
 }
 
 static struct smbus_bus_operations lops_smbus_bus = {
-	.read_byte	= smbus_read_byte,
+	.read_byte	= lsmbus_read_byte,
 };
 
 static const struct device_operations smbus_ops = {
@@ -46,7 +49,7 @@ static const struct device_operations smbus_ops = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= 0,
 	.scan_bus		= scan_static_bus,
-	.enable			= i82801er_enable,
+	.enable			= i82801ax_enable,
 	.ops_smbus_bus		= &lops_smbus_bus,
 };
 
diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.h b/src/southbridge/intel/i82801ax/i82801ax_smbus.h
index d3f49f9a71..312d0b7812 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_smbus.h
+++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.h
@@ -25,7 +25,7 @@ static void smbus_delay(void)
 	inb(0x80);
 }
 
-static int smbus_wait_until_ready(void)
+static int smbus_wait_until_ready(u16 smbus_io_base)
 {
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;
@@ -33,12 +33,12 @@ static int smbus_wait_until_ready(void)
 		smbus_delay();
 		if (--loops == 0)
 			break;
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		byte = inb(smbus_io_base + SMBHSTSTAT);
 	} while (byte & 1);
 	return loops ? 0 : -1;
 }
 
-static int smbus_wait_until_done(void)
+static int smbus_wait_until_done(u16 smbus_io_base)
 {
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;
@@ -46,131 +46,54 @@ static int smbus_wait_until_done(void)
 		smbus_delay();
 		if (--loops == 0)
 			break;
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		byte = inb(smbus_io_base + SMBHSTSTAT);
 	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
 	return loops ? 0 : -1;
 }
 
-static int smbus_wait_until_blk_done(void)
-{
-	unsigned loops = SMBUS_TIMEOUT;
-	unsigned char byte;
-	do {
-		smbus_delay();
-		if (--loops == 0)
-			break;
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	} while ((byte & (1 << 7)) == 0);
-	return loops ? 0 : -1;
-}
-
-static int do_smbus_read_byte(unsigned device, unsigned address)
+static int do_smbus_read_byte(u16 smbus_io_base, unsigned device,
+			      unsigned address)
 {
 	unsigned char global_status_register;
 	unsigned char byte;
 
-	if (smbus_wait_until_ready() < 0) {
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
 	/* Setup transaction */
 	/* Disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
 	/* Set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
 	/* Set the command/address... */
-	outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
 	/* Set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
-	     (SMBUS_IO_BASE + SMBHSTCTL));
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_io_base + SMBHSTCTL));
 	/* Clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
 
 	/* Clear the data byte... */
-	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
+	outb(0, smbus_io_base + SMBHSTDAT0);
 
 	/* Start the command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
-	     SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40),
+	     smbus_io_base + SMBHSTCTL);
 
 	/* Poll for transaction completion */
-	if (smbus_wait_until_done() < 0) {
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 	}
 
-	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
 
 	/* Ignore the "In Use" status... */
 	global_status_register &= ~(3 << 5);
 
 	/* Read results of transaction */
-	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
+	byte = inb(smbus_io_base + SMBHSTDAT0);
 	if (global_status_register != (1 << 1)) {
 		return SMBUS_ERROR;
 	}
 	return byte;
 }
-
-static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
-				unsigned data1, unsigned data2)
-{
-	unsigned char byte;
-	unsigned char stat;
-	int i;
-
-	print_err("Untested smbus_write_block called\n");
-
-	/* Clear the PM timeout flags, SECOND_TO_STS */
-	outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66);
-
-	if (smbus_wait_until_ready() < 0) {
-		return -2;
-	}
-
-	/* Setup transaction */
-	/* Obtain ownership */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	for (stat = 0; (stat & 0x40) == 0;) {
-		stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-	/* Clear the done bit */
-	outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
-	/* Disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* Set the device I'm talking too */
-	outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-
-	/* Set the command address */
-	outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
-
-	/* Set the block length */
-	outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0);
-
-	/* Try sending out the first byte of data here */
-	byte = (data1 >> (0)) & 0x0ff;
-	outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
-	/* Issue a block write command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40,
-	     SMBUS_IO_BASE + SMBHSTCTL);
-
-	for (i = 0; i < length; i++) {
-		/* Poll for transaction completion */
-		if (smbus_wait_until_blk_done() < 0) {
-			return -3;
-		}
-
-		/* Load the next byte */
-		if (i > 3)
-			byte = (data2 >> (i % 4)) & 0x0ff;
-		else
-			byte = (data1 >> (i)) & 0x0ff;
-		outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
-
-		/* Clear the done bit */
-		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
-		     SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-
-	print_debug("SMBUS Block complete\n");
-	return 0;
-}