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| author | Yidi Lin <yidi.lin@mediatek.com> | 2016-03-14 10:06:46 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-18 18:57:17 +0100 |
| commit | 39e55209dce7d971c2e5b53706c5124e1ec01bb3 (patch) | |
| tree | f12478670e294afd3ba86802315fd34dff4dc72c /src/southbridge/intel/i82801ax/pci.c | |
| parent | aad2903c9ceefa9ffb86660c07a7b3eb1ead46b5 (diff) | |
google/oak: Enable RAM_CODE_SUPPORT
BRANCH=none
BUG=chrome-os-partner:50820
TEST=check /proc/device-tree/firmware/coreboot/ram-code
Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361
Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332564
Original-Reviewed-by: Milton Chiang <milton.chiang@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14104
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801ax/pci.c')
0 files changed, 0 insertions, 0 deletions