Round 2 of i82801AX fixes to get it into a usable shape.

 - Remove left-overs from more generic code in i82801xx times, and fix
   register names as needed.
 
 - Simplify IDE init code (and save some ROM space too).
 
 - Simplify PIRQ code.
 
 - Use u8 et al instead of uint8_t everywhere.
 
 - Random other fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 17 insertions, 31 deletions

diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h
index 2ead33f02a..585de6e3c4 100644
--- a/src/southbridge/intel/i82801ax/i82801ax.h
+++ b/src/southbridge/intel/i82801ax/i82801ax.h
@@ -26,37 +26,36 @@
 extern void i82801ax_enable(device_t dev);
 #endif
 
+#define SMBUS_IO_BASE		0x0f00
+#define PMBASE_ADDR		0x0400
+#define HPET_ADDR		0xfed00000
+
 #define PCI_DMA_CFG		0x90
 #define SERIRQ_CNTL		0x64
 #define GEN_CNTL		0xd0
-#define GEN_STS			0xd4
+#define GEN_STA			0xd4
 #define RTC_CONF		0xd8
 #define GEN_PMCON_3		0xa4
 
 #define PMBASE			0x40
-#define PMBASE_ADDR		0x0400 /* ACPI Base Address Register */
 #define ACPI_CNTL		0x44
+#define ACPI_EN			(1 << 4)
 #define BIOS_CNTL		0x4E
-#define GPIO_BASE_ICH0_5	0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
-#define GPIO_BASE_ICH6_9	0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */
-#define GPIO_CNTL_ICH0_5	0x5C /* LPC GPIO Control Register (ICH0-ICH5) */
-#define GPIO_CNTL_ICH6_9	0x4C /* LPC GPIO Control Register (ICH6-ICH9) */
+#define GPIO_BASE		0x58 /* GPIO Base Address Register */
+#define GPIO_CNTL		0x5C /* GPIO Control Register */
+#define GPIO_EN			(1 << 4)
 
 #define PIRQA_ROUT		0x60
 #define PIRQB_ROUT		0x61
 #define PIRQC_ROUT		0x62
 #define PIRQD_ROUT		0x63
-#define PIRQE_ROUT		0x68
-#define PIRQF_ROUT		0x69
-#define PIRQG_ROUT		0x6A
-#define PIRQH_ROUT		0x6B
 
 #define FUNC_DIS		0xF2
 
-#define COM_DEC			0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */
-#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register (ICH6-ICH9) */
-#define LPC_EN_ICH0_5		0xE6 /* LPC IF Enables Register (ICH0-ICH5) */
-#define LPC_EN_ICH6_9		0x82 /* LPC IF Enables Register (ICH6-ICH9) */
+#define COM_DEC			0xE0 /* LPC I/F Comm. Port Decode Ranges */
+#define LPC_EN			0xE6 /* LPC IF Enables */
+
+// TODO: FDC_DEC etc.
 
 #define SBUS_NUM		0x19
 #define SUB_BUS_NUM		0x1A
@@ -77,14 +76,14 @@ extern void i82801ax_enable(device_t dev);
 #define RTC_POWER_FAILED	(1 << 1)
 #define SLEEP_AFTER_POWER_FAIL	(1 << 0)
 
-/* PCI Configuration Space (D31:F1) */
+/* IDE Timing registers (IDE_TIM) */
 #define IDE_TIM_PRI		0x40	/* IDE timings, primary */
 #define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
 
 /* IDE_TIM bits */
 #define IDE_DECODE_ENABLE	(1 << 15)
 
-/* PCI Configuration Space (D31:F3) */
+/* SMBus */
 #define SMB_BASE		0x20
 #define HOSTC			0x40
 
@@ -93,13 +92,7 @@ extern void i82801ax_enable(device_t dev);
 #define SMB_SMI_EN		(1 << 1)
 #define HST_EN			(1 << 0)
 
-/* SMBus I/O bits.
- * TODO: Does it matter where we put the SMBus IO base, as long as we keep
- * consistent and don't interfere with anything else?
- */
-/* #define SMBUS_IO_BASE 0x1000 */
-#define SMBUS_IO_BASE		0x0f00
-
+/* SMBus I/O registers. */
 #define SMBHSTSTAT		0x0
 #define SMBHSTCTL		0x2
 #define SMBHSTCMD		0x3
@@ -107,14 +100,7 @@ extern void i82801ax_enable(device_t dev);
 #define SMBHSTDAT0		0x5
 #define SMBHSTDAT1		0x6
 #define SMBBLKDAT		0x7
-#define SMBTRNSADD		0x9
-#define SMBSLVDATA		0xa
-#define SMLINK_PIN_CTL		0xe
-#define SMBUS_PIN_CTL		0xf
 
 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
 
-/* HPET, if present */
-#define HPET_ADDR		0xfed00000
-
-#endif				/* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */
+#endif