diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-13 01:41:00 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 13:22:44 +0000 |
| commit | 3eb8dbaee2eac62438b6c5391c09979bcaed32b0 (patch) | |
| tree | e80d10e66432d7450c12c7598be70e7cd8d60604 /src/southbridge/intel/i82371eb | |
| parent | b74975e40364ce3b66bda54167ca20cdf6cbda35 (diff) | |
src: Drop useless cache flush settings in FADT
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/fadt.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index c775af0c92..249b22b5bc 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -38,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ - fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */ - fadt->flush_stride = 0; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ |