diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-06-19 10:49:29 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-03 01:29:01 +0100 |
| commit | 4bdc4aa297150f4b8913f43df8286671886aca3e (patch) | |
| tree | 508c5f27e22013669da59e774f58b5119e3349db /src/southbridge/intel/i82371eb | |
| parent | a392d477c10d587a1c3de29c3c3e6c56a7fcafdd (diff) | |
lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
LynxPoint-LP has a lot of GPEs and the "default" set has been
moved to register 4 starting at bit offset 96. This means
that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP
but still bit 13 in LPT-H.
suspend on falco and wake from usb
4 | 2013-06-19 10:49:17 | ACPI Enter | S3
5 | 2013-06-19 10:49:22 | ACPI Wake | S3
6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0
Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59265
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4253
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/i82371eb')
0 files changed, 0 insertions, 0 deletions