diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-16 10:01:33 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 14:10:00 +0000 |
| commit | 2119d0ba4345a19b9db7dc13e36f3fa57f75d234 (patch) | |
| tree | aeeef324906730e350c338edb4f5704f20a95385 /src/southbridge/intel/i82371eb | |
| parent | ebdf298ec2dd84810a37a4aac154200b2102b394 (diff) | |
treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/fadt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index cbfb0af2ee..15ab0eec0d 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -80,7 +80,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->flush_stride = 0; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */ + fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ fadt->mon_alrm = 0x0; /* not supported */ fadt->century = 0x0; /* not supported */ /* |