first round name simplification. drop the <component>_ prefix.

the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 147 insertions, 0 deletions

diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
new file mode 100644
index 0000000000..d025bf2393
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/isa-dma.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
+#include "i82371eb.h"
+
+#if CONFIG_IOAPIC
+static void enable_intel_82093aa_ioapic(void)
+{
+	u16 reg16;
+	u32 reg32;
+	u8 ioapic_id = 2;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+	device_t dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+			      PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
+
+	/* Enable IOAPIC. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= (1 << 8); /* APIC Chip Select */
+	pci_write_config16(dev, XBCS, reg16);
+
+	/* Set the IOAPIC ID. */
+	*ioapic_index = 0;
+	*ioapic_data = ioapic_id << 24;
+
+	/* Read back and verify the IOAPIC ID. */
+	*ioapic_index = 0;
+	reg32 = (*ioapic_data >> 24) & 0x0f;
+	printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
+	if (reg32 != ioapic_id)
+		die("IOAPIC error!\n");
+}
+#endif
+
+static void isa_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Initialize the real time clock (RTC). */
+	rtc_init(0);
+
+	/*
+	 * Enable special cycles, needed for soft poweroff.
+	 */
+	reg32 = pci_read_config16(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_SPECIAL;
+	pci_write_config16(dev, PCI_COMMAND, reg32);
+
+	/*
+	 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
+	 * bus, which is a subset of ISA. We select the full ISA bus here.
+	 */
+	reg32 = pci_read_config32(dev, GENCFG);
+	reg32 |= ISA;	/* Select ISA, not EIO. */
+	pci_write_config16(dev, GENCFG, reg32);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+#if CONFIG_IOAPIC
+	/*
+	 * Unlike most other southbridges the 82371EB doesn't have a built-in
+	 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
+	 * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
+	 *
+	 * Thus, we can/must only enable the IOAPIC if it actually exists,
+	 * i.e. the respective mainboard does "select IOAPIC".
+	 */
+	enable_intel_82093aa_ioapic();
+#endif
+}
+
+static void sb_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 2);
+	res->base = 0xff800000UL;
+	res->size = 0x00800000UL; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		IORESOURCE_RESERVE;
+
+#if CONFIG_IOAPIC
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		IORESOURCE_RESERVE;
+#endif
+}
+
+static const struct device_operations isa_ops = {
+	.read_resources		= sb_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= isa_init,
+	.scan_bus		= scan_static_bus,	/* TODO: Needed? */
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+};
+
+static const struct pci_driver isa_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_ISA,
+};
+
+static const struct pci_driver isa_SB_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_ISA,
+};