Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):

 - Implement ISA related support:
   - Initialize the RTC
   - Enable access to all BIOS regions (but _not_ write access to ROM)
   - Enable ISA (not EIO) support
   - Without the *_isa.c file, the Super I/O init is never performed
 - Improve IDE support:
   - Add config option to enable Ultra DMA/33 for each disk
   - Add config option to enable legacy IDE port access
 - Implement hard reset support
 - Implement USB controller support
 - Various code cleanups and improvements

The code partially supports southbridges other than the 82371EB (but
which are very similar), more complete support will follow.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 9 insertions, 7 deletions

diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index 30b6e6a320..fc6e199ea6 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -20,6 +20,7 @@
 
 /* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */
 
+#include <stdint.h>
 #include <device/pci_ids.h>
 #include "i82371eb.h"
 #include "i82371eb_smbus.h"
@@ -29,35 +30,36 @@
 static void enable_smbus(void)
 {
 	device_t dev;
-	uint8_t reg8;
-	uint16_t reg16;
+	u8 reg8;
+	u16 reg16;
 
+	/* Check for SMBus device PCI ID on the 82371AB/EB/MB. */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
 				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
 
-	if (dev == PCI_DEV_INVALID) {
+	if (dev == PCI_DEV_INVALID)
 		die("SMBus controller not found\r\n");
-	}
+
 	print_spew("SMBus controller enabled\r\n");
 
 	/* Set the SMBus I/O base. */
 	pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
 
-	/* Enable the SMBus Controller Host Interface. */
+	/* Enable the SMBus controller host interface. */
 	reg8 = pci_read_config8(dev, SMBHSTCFG);
 	reg8 |= SMB_HST_EN;
 	pci_write_config8(dev, SMBHSTCFG, reg8);
 
 	/* Enable access to the SMBus I/O space. */
 	reg16 = pci_read_config16(dev, PCI_COMMAND);
-	reg16 |= IOSE;
+	reg16 |= PCI_COMMAND_IO;
 	pci_write_config16(dev, PCI_COMMAND, reg16);
 
 	/* Clear any lingering errors, so the transaction will run. */
 	outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
 }
 
-static int smbus_read_byte(unsigned int device, unsigned int address)
+static int smbus_read_byte(u8 device, u8 address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }