After finding the missing bit poweroff works now.

I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates suggestions
on irc by uwe (thanks for the comments).
Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.

Tested:
  Linux (poweroff, powerbutton event)
  XP (poweroff, powerbutton event)

Abuild-tested

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 49 insertions, 2 deletions

diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 0536c54541..a77a8e68aa 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -56,14 +56,61 @@ void i82371eb_hard_reset(void);
 
 /* SMBus */
 #define SMBBA		0x90	/* SMBus base address */
+#define   SMBUS_IO_BASE	0x0f00
 #define SMBHSTCFG	0xd2	/* SMBus host configuration */
 
 /* Power management (ACPI) */
+#define PMSTS		0x00	/* Power Management Status */
+#define PMEN		0x02	/* Power Management Resume Enable */
+#define   PWRBTN_EN	(1<<8)
+#define   GBL_EN	(1<<5)
+#define PMCNTRL		0x04	/* Power Management Control */
+#define   SUS_EN	(1<<13)	/* S0-S5 trigger */
+#define   SUS_TYP_MSK	(7<<10)
+#define   SUS_TYP_S0	(5<<10)
+#define   SUS_TYP_S1	(4<<10)
+#define   SUS_TYP_S2	(3<<10)
+//#define   SUS_TYP_S2>---(2<<10)
+#define   SUS_TYP_S3	(1<<10)
+#define   SUS_TYP_S5	(0<<10)
+#define   SCI_EN	(1<<0)
+#define PMTMR		0x08	/* Power Management Timer */
+#define GPSTS		0x0c	/* General Purpose Status */
+#define GPEN		0x0e	/* General Purpose Enable */
+#define   THRM_EN	(1<<0)
+#define PCNTRL		0x10	/* Processor control */
+#define GLBSTS		0x18	/* Global Status */
+#define   IRQ_RSM_STS	(1<<11)
+#define   EXTSMI_STS	(1<<10)
+#define   GSTBY_STS	(1<<8)
+#define   GP_STS	(1<<7)
+#define   BM1_STS	(1<<6)
+#define   APM_STS	(1<<5)
+#define   DEV_STS	(1<<4)
+#define   BIOS_EN	(1<<1)	/* GBL_RLS write triggers SMI */
+#define   LEGACY_USB_EN	(1<<0)	/* Keyboard controller access triggers SMI */
+#define DEVSTS		0x1c	/* Device Status */
+#define GLBEN		0x20	/* Global Enable */
+#define   EXTSMI_EN	(1<<10)	/* EXTSMI# signal triggers SMI */
+#define   GSTBY_EN	(1<<8)
+#define   BM_TRP_EN	(1<<1)
+#define   BIOS_EN	(1<<1)	/* GBL_RLS write triggers SMI */
+#define   LEGACY_USB_EN	(1<<0)	/* Keyboard controller access triggers SMI */
+#define GLBCTL		0x28	/* Global Control */
+#define   EOS		(1<<16)	/* End of SMI */
+#define   SMI_EN	(1<<0)	/* SMI enable */
+#define DEVCTL		0x2c	/* Device Control */
+#define   TRP_EN_DEV12	(1<<24)	/* SMI on dev12 trap */
+#define GPO0		0x34
+#define GPO1		0x35
+#define GPO2		0x36
+#define GPO3		0x37
+
 #define PMBA		0x40	/* Power management base address */
+#define   DEFAULT_PMBASE	0xe400
+#define   PM_IO_BASE DEFAULT_PMBASE
 #define PMREGMISC	0x80	/* Miscellaneous power management */
 
-#define PM_IO_BASE	0xe400
-
 /* Bit definitions */
 #define EXT_BIOS_ENABLE_1MB	(1 << 9)  /* 1-Meg Extended BIOS Enable */
 #define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */