diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-11-30 02:08:26 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-11-30 02:08:26 +0000 |
| commit | 9da69f83d9fd3b872afb38c24b373b0807c76b00 (patch) | |
| tree | 10f1597c46c6dcfcf125953421c61fe8c5aebf64 /src/southbridge/intel/i82371eb/chip.h | |
| parent | 8d43b343cf390f67461b3121d101d16ebf9b5975 (diff) | |
Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):
- Implement ISA related support:
- Initialize the RTC
- Enable access to all BIOS regions (but _not_ write access to ROM)
- Enable ISA (not EIO) support
- Without the *_isa.c file, the Super I/O init is never performed
- Improve IDE support:
- Add config option to enable Ultra DMA/33 for each disk
- Add config option to enable legacy IDE port access
- Implement hard reset support
- Implement USB controller support
- Various code cleanups and improvements
The code partially supports southbridges other than the 82371EB (but
which are very similar), more complete support will follow.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb/chip.h')
| -rw-r--r-- | src/southbridge/intel/i82371eb/chip.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h index 2dac6d14ec..7f6cbaa6fb 100644 --- a/src/southbridge/intel/i82371eb/chip.h +++ b/src/southbridge/intel/i82371eb/chip.h @@ -23,12 +23,17 @@ #include <device/device.h> -extern struct chip_operations southbridge_intel_i82371eb_ops; +extern const struct chip_operations southbridge_intel_i82371eb_ops; struct southbridge_intel_i82371eb_config { int ide0_enable:1; + int ide0_drive0_udma33_enable:1; + int ide0_drive1_udma33_enable:1; int ide1_enable:1; + int ide1_drive0_udma33_enable:1; + int ide1_drive1_udma33_enable:1; + int ide_legacy_enable:1; int usb_enable:1; }; -#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */ |