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| author | Aaron Durbin <adurbin@chromium.org> | 2015-03-06 23:17:33 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-04-22 17:55:08 +0200 |
| commit | bd74a4b2d25268f7035a4478da31f27baac2aecc (patch) | |
| tree | 56740c02fe396df8ccf9fc2e7401542deeebf453 /src/southbridge/intel/i3100 | |
| parent | cac50506238507328b8ea0f4abd458869803e6c2 (diff) | |
coreboot: common stage cache
Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.
Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/i3100')
0 files changed, 0 insertions, 0 deletions