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author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-24 20:22:28 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2016-04-26 16:53:42 +0200 |
commit | 3242bcfa0feb50160dc0e6059216a5c1a0626031 (patch) | |
tree | 0202aed7ef412b285aed4255e898dff65e4237d7 /src/southbridge/intel/i3100/pci.c | |
parent | c1b98b909c1d3bbd4eb74140769b118c98a9eb70 (diff) |
nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup
The existing RDIMM RC control word send routines were a hodgepodge
of various AGESA chunks with different ways of handling the same
task. Unify the control word chip select setup, use precise timing
routines on Family 15h, fix a couple of incorrect masks, and add
additional debugging statements.
It is believed that this patch is cosmetic and does not significantly
alter existing functionality.
Change-Id: Ie4ec7b6a7be7fce09e89f9eec146cc98b15b6160
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14500
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i3100/pci.c')
0 files changed, 0 insertions, 0 deletions