diff options
author | Aaron Durbin <adurbin@chromium.org> | 2013-02-15 23:26:52 -0600 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 22:59:40 +0100 |
commit | de1f890186ce84963eb3dd1638784473193909c3 (patch) | |
tree | 1ad9b1358d208bc338f4766a117fe5e076a84cef /src/southbridge/intel/i3100/pci.c | |
parent | 8ce667e50684bea7c60db43c0ca7dd1b3ec3fde3 (diff) |
coreboot: add caching loaded ramstage interface
Instead of hard coding the policy for how a relocated ramstage
image is saved add an interface. The interface consists of two
functions. cache_loaded_ramstage() and load_cached_ramstage()
are the functions to cache and load the relocated ramstage,
respectively. There are default implementations which cache and
load the relocated ramstage just below where the ramstage runs.
Change-Id: I4346e873d8543e7eee4c1cd484847d846f297bb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2805
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i3100/pci.c')
0 files changed, 0 insertions, 0 deletions