diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-01 16:56:36 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 16:01:35 +0000 |
commit | 551a75923ec7e7bacaf6da79b38eda5c3b3821ad (patch) | |
tree | 32d10123e44a9e7e8c699e532b2c8fe8f2ac781c /src/southbridge/intel/fsp_rangeley | |
parent | 30bc9f415d9564de90fc0c6c6a92462ce3ce7c06 (diff) |
sb/{ICH7,NM10,PCH}: Use common watchdog_off function
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/Kconfig | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/Makefile.inc | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/watchdog.c | 53 |
3 files changed, 1 insertions, 54 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index c15c48d445..4526cb3cf5 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -31,6 +31,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index ac5888ca38..7fc86012de 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -19,7 +19,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) ramstage-y += soc.c ramstage-y += lpc.c ramstage-y += sata.c -ramstage-y += watchdog.c ramstage-y += spi.c ramstage-y += smbus.c ramstage-y += acpi.c diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c deleted file mode 100644 index f18af8927c..0000000000 --- a/src/southbridge/intel/fsp_rangeley/watchdog.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <device/device.h> -#include <device/pci.h> -#include <watchdog.h> -#include "soc.h" - -void watchdog_off(void) -{ - struct device *dev; - u32 value, abase; - - /* Turn off the watchdog. */ - dev = pcidev_on_root(0x1f, 0); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= 1; - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - abase = (pci_read_config32(dev, ABASE) & ~0xf); - - /* Disable the watchdog timer. */ - value = inw(abase + 0x68); - value |= 1 << 11; - outw(value, abase + 0x68); - - /* Clear TCO timeout status. */ - outw(0x0008, abase + 0x64); - outw(0x0002, abase + 0x66); - - printk(BIOS_DEBUG, "TCO Watchdog disabled\n"); -} |