diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:25:50 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:34:22 +0200 |
| commit | 4d7a9a556934b06f27e88810ff2f1e6bd522eb40 (patch) | |
| tree | 0a80a01e2788c3d092304ae2b1920e13f26de668 /src/southbridge/intel/fsp_rangeley | |
| parent | e99194555b9cb07bacc3008ec78ec61a949b47b9 (diff) | |
southbridge/intel/fsp_rangeley: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Ia113672fa3cb740cb193c23fd06181d9ce895ac3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.h | 9 |
2 files changed, 3 insertions, 7 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 919d963c54..092cf1dd63 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -21,6 +21,7 @@ if SOUTHBRIDGE_INTEL_FSP_RANGELEY config SOUTH_BRIDGE_OPTIONS # dummy def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC select HAVE_HARD_RESET select HAVE_USBDEBUG diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index ba0fa4e8c5..0674dcae4f 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -18,6 +18,8 @@ #ifndef SOUTHBRIDGE_INTEL_RANGELEY_SOC_H #define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H +#include <arch/acpi.h> + /* SOC types */ #define SOC_TYPE_RANGELEY 0x1F @@ -316,13 +318,6 @@ void rangeley_sb_early_initialization(void); #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) |