summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/fsp_rangeley
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-18 15:26:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-03-27 08:26:16 +0000
commitf5cf60f25b8c77e0c90094e3326c5bc0e37cb383 (patch)
tree63967d01ebab0c1cdb41c58d4c52fea1d45616a4 /src/southbridge/intel/fsp_rangeley
parent12724d6ad6fd6ab0ca8ea5d258c0ca7cce807441 (diff)
Move calls to quick_ram_check() before CBMEM init
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 14611b3891..19e470e309 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
#include <device/mmio.h>
@@ -114,9 +113,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
/* Decode E0000 and F0000 segment to DRAM */
sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));
- quick_ram_check();
- post_code(0x4d);
-
cbmem_was_initted = !cbmem_recovery(0);
/* Save the HOB pointer in CBMEM to be used in ramstage*/