diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/fsp_rangeley | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/acpi.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/spi.c | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index e111881581..e0b3cb985c 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <version.h> -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) #include <cpu/x86/smm.h> #endif diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index b93bc09a62..711778e125 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -95,7 +95,7 @@ static void soc_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) write8(ibase + ILB_SERIRQ_CNTL, 0); #endif } @@ -435,7 +435,7 @@ static void southbridge_inject_dsdt(struct device *dev) if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); #endif diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 65001cfff1..2891ca4ae7 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -102,7 +102,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 29ed943d3d..4c5e835c7f 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -61,7 +61,7 @@ void soc_enable(struct device *dev); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void soc_log_state(void); #endif #else diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 99400fcbeb..e65576769c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -193,7 +193,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3, }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { |