x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

7 files changed, 52 insertions, 47 deletions

diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 844f4b8492..e4e7071cd1 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -34,15 +34,15 @@ static void rangeley_setup_bars(void)
 {
 	/* Setting up Southbridge. */
 	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-	pci_write_config32(LPC_BDF, RCBA, DEFAULT_RCBA | RCBA_ENABLE);
+	pci_write_config32(LPC_BDF, RCBA, (uintptr_t)DEFAULT_RCBA | RCBA_ENABLE);
 	pci_write_config32(LPC_BDF, ABASE, DEFAULT_ABASE | SET_BAR_ENABLE);
 	pci_write_config32(LPC_BDF, PBASE, DEFAULT_PBASE | SET_BAR_ENABLE);
 	printk(BIOS_DEBUG, " done.\n");
 
 	printk(BIOS_DEBUG, "Disabling Watchdog timer...");
 	/* Disable the watchdog reboot and turn off the watchdog timer */
-	write8(DEFAULT_PBASE + PMC_CFG, read8(DEFAULT_PBASE + PMC_CFG) |
-		 NO_REBOOT);	// disable reboot on timer trigger
+	write8((void *)(DEFAULT_PBASE + PMC_CFG),
+	       read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT);	// disable reboot on timer trigger
 	outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) |
 		TCO_TMR_HALT);	// disable watchdog timer
 
@@ -54,7 +54,7 @@ static void reset_rtc(void)
 {
 	uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) &
 		0xfffffff0;
-	uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+	uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1));
 	int rtc_failed = !!(gen_pmcon1 & RPS);
 
 	if (rtc_failed) {
@@ -63,7 +63,8 @@ static void reset_rtc(void)
 			coreboot_dmi_date);
 
 		/* Clear the power failure flag */
-		write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+		write32((void *)(DEFAULT_PBASE + GEN_PMCON1),
+			gen_pmcon1 & ~RPS);
 	}
 
 	cmos_init(rtc_failed);
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 8569b967d4..6ea9c2e7e5 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -30,7 +30,7 @@
 void setup_soc_gpios(const struct soc_gpio_map *gpio)
 {
 	u16 gpiobase = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf;
-	u32 cfiobase = pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf;
+	u32 *cfiobase = (u32 *)(pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf);
 	u32 cfio_cnt = 0;
 
 
@@ -67,30 +67,30 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
 	/* GPIO PAD settings */
 	/* CFIO Core Well Set 1 */
 	if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
-		write32(cfiobase + 0x0700, (u32)0x01001002);
+		write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
 		for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
 			if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
 				continue;
-			write32(cfiobase + CFIO_PAD_CONF0 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
-			write32(cfiobase + CFIO_PAD_CONF1 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
-			write32(cfiobase + CFIO_PAD_VAL + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
-			write32(cfiobase + CFIO_PAD_DFT + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
+			write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
+			write32(cfiobase + ((CFIO_PAD_CONF1 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
+			write32(cfiobase + ((CFIO_PAD_VAL + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
+			write32(cfiobase + ((CFIO_PAD_DFT + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
 		}
-		write32(cfiobase + 0x0700, (u32)0x01041002);
+		write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01041002);
 	}
 
 	/* CFIO SUS Well Set 1 */
 	if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
-		write32(cfiobase + 0x1700, (u32)0x01001002);
+		write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
 		for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
 			if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
 				continue;
-			write32(cfiobase + CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
-			write32(cfiobase + CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
-			write32(cfiobase + CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
-			write32(cfiobase + CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
+			write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
+			write32(cfiobase + ((CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
+			write32(cfiobase + ((CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
+			write32(cfiobase + ((CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
 		}
-		write32(cfiobase + 0x1700, (u32)0x01041002);
+		write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01041002);
 	}
 }
 
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 9644067971..8f2967048a 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev)
 	u32 reg32;
 	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
 	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-	u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f;
+	u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f);
 
 	/*
 	 * Enable ACPI I/O and power management.
@@ -91,9 +91,9 @@ static void soc_enable_apic(struct device *dev)
 
 static void soc_enable_serial_irqs(struct device *dev)
 {
-	u32 ibase;
+	u8 *ibase;
 
-	ibase = pci_read_config32(dev, IBASE) & ~0xF;
+	ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
 
 	/* Set packet length and toggle silent mode bit for one frame. */
 	write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
@@ -206,10 +206,10 @@ static void soc_pirq_init(device_t dev)
 {
 	int i, j;
 	int pirq;
-	const u32 ibase = pci_read_config32(dev, IBASE) & ~0xF;
-	const unsigned long pr_base = ibase + 0x08;
-	const unsigned long ir_base = ibase + 0x20;
-	const unsigned long actl = ibase;
+	u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
+	u8 *pr_base = ibase + 0x08;
+	u16 *ir_base = (u16 *)(ibase + 0x20);
+	u32 *actl = (u32 *)ibase;
 	const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
 
 	/* Set up the PIRQ PIC routing based on static config. */
@@ -226,7 +226,7 @@ static void soc_pirq_init(device_t dev)
 	printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
 			"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
 	for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
-		write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+		write16(ir_base + i, ir->pcidev[i]);
 
 		/* If the entry is more than just 0, print it out */
 		if(ir->pcidev[i]) {
@@ -293,10 +293,10 @@ static void soc_power_options(device_t dev)
 /* Disable the HPET, Clear the counter, and re-enable it. */
 static void enable_hpet(void)
 {
-	write8(HPET_GCFG, 0x00);
-	write32(HPET_MCV, 0x00000000);
-	write32(HPET_MCV + 0x04, 0x00000000);
-	write8(HPET_GCFG, 0x01);
+	write8((u8 *)HPET_GCFG, 0x00);
+	write32((u32 *)HPET_MCV, 0x00000000);
+	write32((u32 *)(HPET_MCV + 0x04), 0x00000000);
+	write8((u8 *)HPET_GCFG, 0x01);
 }
 
 static void soc_disable_smm_only_flashing(struct device *dev)
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index a668815fe8..e6b4f62d7e 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -42,7 +42,7 @@
 void main(FSP_INFO_HEADER *fsp_info_header)
 {
 	uint32_t fd_mask = 0;
-	uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;
+	uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS);
 
 	/*
 	 * Do not use the Serial Console before it is setup.
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index f672e4c428..4648ac7467 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -32,7 +32,7 @@ static void sata_init(struct device *dev)
 {
 	u32 reg32;
 	u16 reg16;
-	u32 abar;
+	u32 *abar;
 
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
@@ -74,13 +74,13 @@ static void sata_init(struct device *dev)
 		pci_write_config16(dev, SATA_MAP, reg16);
 
 		/* Initialize AHCI memory-mapped space */
-		abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-		printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+		abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+		printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 
 		/* Enable AHCI Mode */
-		reg32 = read32(abar + 0x04);
+		reg32 = read32(abar + 0x01);
 		reg32 |= (1 << 31);
-		write32(abar + 0x04, reg32);
+		write32(abar + 0x01, reg32);
 	} else {
 		printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
 	}
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 6db4b11da3..f1b1781afc 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -43,7 +43,11 @@
 /* Southbridge internal device MEM BARs (Set to match FSP settings) */
 #define DEFAULT_IBASE		0xfed08000
 #define DEFAULT_PBASE		0xfed03000
+#ifndef __ACPI__
+#define DEFAULT_RCBA		((u8 *)0xfed1c000)
+#else
 #define DEFAULT_RCBA		0xfed1c000
+#endif
 
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index ee22019ade..b813d0763e 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -231,7 +231,7 @@ enum {
 
 static u8 readb_(const void *addr)
 {
-	u8 v = read8((unsigned long)addr);
+	u8 v = read8(addr);
 	printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
 	       v, ((unsigned) addr & 0xffff) - 0xf020);
 	return v;
@@ -239,7 +239,7 @@ static u8 readb_(const void *addr)
 
 static u16 readw_(const void *addr)
 {
-	u16 v = read16((unsigned long)addr);
+	u16 v = read16(addr);
 	printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
 	       v, ((unsigned) addr & 0xffff) - 0xf020);
 	return v;
@@ -247,7 +247,7 @@ static u16 readw_(const void *addr)
 
 static u32 readl_(const void *addr)
 {
-	u32 v = read32((unsigned long)addr);
+	u32 v = read32(addr);
 	printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
 	       v, ((unsigned) addr & 0xffff) - 0xf020);
 	return v;
@@ -255,14 +255,14 @@ static u32 readl_(const void *addr)
 
 static void writeb_(u8 b, const void *addr)
 {
-	write8((unsigned long)addr, b);
+	write8(addr, b);
 	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 static void writew_(u16 b, const void *addr)
 {
-	write16((unsigned long)addr, b);
+	write16(addr, b);
 	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
@@ -276,12 +276,12 @@ static void writel_(u32 b, const void *addr)
 
 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
 
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
 
 #endif  /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */