diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/intel/fsp_rangeley | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/acpi/soc.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index 696a81ae65..b55bd92dd1 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -208,7 +208,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) |