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authornicky sielicki <nlsielicki@wisc.edu>2015-04-09 20:21:56 -0500
committerMartin Roth <gaumless@gmail.com>2015-04-10 17:57:11 +0200
commit1376b680c24025234e8bad0e7982dfca4dc1afec (patch)
treee45460d167c7058b134a959c0133a4b6fcb002e6 /src/southbridge/intel/fsp_rangeley/soc.c
parent1483822ab8a1748b18b4a41e24db2381121c04ef (diff)
southbridge/intel/fsp_rangeley/ : Spellcheck + Formatting
Changes: acpi.c - Capitalize an acronym. early_spi.c - Spelling error. gpio.c - Capitalization of acronym + sentences. gpio.h - Capitalization of sentences. lpc.c - Capitalization of sentences. soc.c - Spelling error + capitalization of acronym. I just wanted to go through the process of commiting something onto Gerrit. Change-Id: Iad2ac5409f883c5b7cbc25e4e296f386ad7e13d0 Signed-off-by: nicky sielicki <nlsielicki@wisc.edu> Reviewed-on: http://review.coreboot.org/9510 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/soc.c')
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index fa03ccdf2a..4e443c51dc 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -61,7 +61,7 @@ int soc_silicon_supported(int type, int rev)
return 0;
}
-/* Set bit in Function Disble register to hide this device */
+/* Set bit in Function Disable register to hide this device */
static void soc_hide_devfn(unsigned devfn)
{
/* TODO Function Disable. */
@@ -77,7 +77,7 @@ void soc_enable(device_t dev)
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
- /* Ensure memory, io, and bus master are all disabled */
+ /* Ensure memory, IO, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);