diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-13 13:22:58 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-22 07:21:07 +0000 |
commit | cbcdb3e754a2d1c68928725d37ccf1621d936a74 (patch) | |
tree | 1c0d63da5a7c5165eb5aa4b82898ca54e31c2b21 /src/southbridge/intel/fsp_rangeley/lpc.c | |
parent | 4ccb23fe27bc9fa45b6db8a7b4ec519a3c25674b (diff) |
sb/intel/fsp_rangeley: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/lpc.c')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index b9af406c1f..a8b87574d3 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -114,8 +114,8 @@ static void soc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -198,7 +198,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void soc_pirq_init(device_t dev) +static void soc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -243,7 +243,7 @@ static void soc_pirq_init(device_t dev) write_pci_config_irqs(); } -static void soc_power_options(device_t dev) +static void soc_power_options(struct device *dev) { u8 reg8; u16 pmbase; @@ -345,7 +345,7 @@ static void lpc_init(struct device *dev) soc_disable_smm_only_flashing(dev); } -static void soc_lpc_read_resources(device_t dev) +static void soc_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -406,17 +406,17 @@ static void soc_lpc_read_resources(device_t dev) } } -static void soc_lpc_enable_resources(device_t dev) +static void soc_lpc_enable_resources(struct device *dev) { return pci_dev_enable_resources(dev); } -static void soc_lpc_enable(device_t dev) +static void soc_lpc_enable(struct device *dev) { soc_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -427,7 +427,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(device_t dev) +static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |