diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:37:28 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:45 +0000 |
| commit | c2c634a089fa990418c363e2ff2e5ff70bdd3580 (patch) | |
| tree | 042e376cee473f72f143ed76768f50536ab323ef /src/southbridge/intel/fsp_rangeley/Kconfig | |
| parent | 298619f6d9adde49b4279c906b0d20a41f919a61 (diff) | |
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/Kconfig')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/Kconfig | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig deleted file mode 100644 index 076a2bce55..0000000000 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Google Inc. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_INTEL_FSP_RANGELEY - bool - -if SOUTHBRIDGE_INTEL_FSP_RANGELEY - -config SOUTH_BRIDGE_OPTIONS # dummy - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select IOAPIC - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select SPI_FLASH - select INTEL_DESCRIPTOR_MODE_CAPABLE - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG - select SOUTHBRIDGE_INTEL_COMMON_PMBASE - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG - -config EHCI_BAR - hex - default 0xfef00000 - -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -config HPET_MIN_TICKS - hex - default 0x80 - -config IFD_BIN_PATH - string - depends on HAVE_IFD_BIN - default "../intel/mainboard/intel/rangeley" - help - The path and filename to the descriptor.bin file. - -endif |