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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-31 19:22:16 +0200
committerMartin Roth <martinroth@google.com>2016-08-31 20:22:46 +0200
commitba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch)
tree9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/intel/fsp_i89xx
parent2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff)
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/fsp_i89xx')
-rw-r--r--src/southbridge/intel/fsp_i89xx/lpc.c2
-rw-r--r--src/southbridge/intel/fsp_i89xx/me.c2
-rw-r--r--src/southbridge/intel/fsp_i89xx/me_8.x.c8
-rw-r--r--src/southbridge/intel/fsp_i89xx/romstage.c2
-rw-r--r--src/southbridge/intel/fsp_i89xx/smihandler.c64
5 files changed, 39 insertions, 39 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c
index 5b8fdbcb6e..1514500e75 100644
--- a/src/southbridge/intel/fsp_i89xx/lpc.c
+++ b/src/southbridge/intel/fsp_i89xx/lpc.c
@@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c
index caf24e30fb..7ea42d4843 100644
--- a/src/southbridge/intel/fsp_i89xx/me.c
+++ b/src/southbridge/intel/fsp_i89xx/me.c
@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index 090d8d0f2b..f25843ed5c 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
print_cap("ICC Over Clocking", cap->icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
print_cap("IPV6", cap->ipv6);
print_cap("KVM Remote Control (KVM)", cap->kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
@@ -670,7 +670,7 @@ static void intel_me_init(device_t dev)
if (intel_mei_setup(dev) < 0)
break;
- if(intel_me_read_mbp(&mbp_data))
+ if (intel_me_read_mbp(&mbp_data))
break;
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
@@ -855,7 +855,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
buffer_room, copy_size, mbp_item_id);
return -1;
}
- while(copy_size--)
+ while (copy_size--)
*copy_addr++ = read_cb();
}
@@ -865,7 +865,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
{
int cntr = 0;
- while(host.interrupt_generate) {
+ while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index c5c1136a43..09cce59444 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -203,7 +203,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
cbmem_was_initted = !cbmem_recovery(0);
- if(cbmem_was_initted) {
+ if (cbmem_was_initted) {
reset_system();
}
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index 27b8166b1c..d4dbb22a94 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
/*
@@ -746,7 +746,7 @@ void southbridge_smi_handler(void)
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}