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| author | Martin Roth <martinroth@google.com> | 2017-06-24 21:29:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-16 19:22:18 +0000 |
| commit | 7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 (patch) | |
| tree | 0db32f6a8f2349b5ce269996f3246b13fec9d5af /src/southbridge/intel/fsp_i89xx/romstage.c | |
| parent | 9fa8ebe1a41fab33badfa4745708e1ad237e8a34 (diff) | |
southbridge/intel: add IS_ENABLED() around Kconfig symbol references
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_i89xx/romstage.c')
| -rw-r--r-- | src/southbridge/intel/fsp_i89xx/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index c2b5221c48..385e4d6ba3 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -137,7 +137,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); post_code(0x46); if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but |