diff options
author | Marc Jones <marc.jones@se-eng.com> | 2015-09-15 12:44:37 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2015-11-10 00:00:46 +0100 |
commit | 5a4554a73f68247c4e00cb1a5d19fb504e9adb92 (patch) | |
tree | b72910ae43f17efcdfc9320d7219f390f961374a /src/southbridge/intel/fsp_i89xx/acpi/pcie_port.asl | |
parent | 721c407caa934ae9dd6e0fa8af0fc547e99d064c (diff) |
southbridge/intel: Add FSP based i89xx southbridge support
The Intel i89xx is a communications chipset that pairs with
Sandy(Ivy)bridge processors. It has a lot in common with
the bd82x6x chipset, but fewer devices and options.
Change-Id: I11bcd1edc80f72a1b2521def9be0d1bde5789a79
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12166
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_i89xx/acpi/pcie_port.asl')
-rw-r--r-- | src/southbridge/intel/fsp_i89xx/acpi/pcie_port.asl | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/acpi/pcie_port.asl b/src/southbridge/intel/fsp_i89xx/acpi/pcie_port.asl new file mode 100644 index 0000000000..276227bb50 --- /dev/null +++ b/src/southbridge/intel/fsp_i89xx/acpi/pcie_port.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Included in each PCIe Root Port device */ + +OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) +Field (RPCS, AnyAcc, NoLock, Preserve) +{ + Offset (0x4c), // Link Capabilities + , 24, + RPPN, 8, // Root Port Number +} |