diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/intel/fsp_bd82x6x | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/me.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/smi.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl index 114aea6021..510749175b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl @@ -202,7 +202,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h index f95a0b46a0..b0f2a6e90b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.h +++ b/src/southbridge/intel/fsp_bd82x6x/me.h @@ -292,7 +292,7 @@ typedef struct { typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; - u16 s3authentication : 1; + u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 wwan3gpresent : 1; @@ -350,7 +350,7 @@ typedef struct { typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __packed mbp_header; typedef struct { diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index 14637e62b3..22489040ae 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -324,7 +324,7 @@ void southbridge_clear_smi_status(void) reset_pm1_status(); /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); + smi_set_eos(); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 90ed943cba..c868ec6cf8 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -659,7 +659,7 @@ static void southbridge_smi_monitor(void) data = RCBA32(0x1e18); data &= mask; // if (smi1) - // southbridge_smi_command(data); + // southbridge_smi_command(data); // return; } // Fall through to debug |